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When we talk of precision instrumentation, we are looking at a system that can manage highly complex math-intensive tasks, since the data collected from physical sensors need a complex degree of calculations to be measured. Although a DSP is well suited for extremely complex math-intensive tasks, it cannot process high sampling rate applications due to its serial architecture.
ASIC does meet all the constraints of digital signal processing, however, it lacks flexibility and requires long design cycles. FPGA overcomes the disadvantages of ASIC and DSP with flexibility, time-to-market, risk-mitigation and lower system costs. FPGA is ideal for implementing data formatting, timing, and specialized glue logic needed to connect real-time peripherals like modems, A/D converters and digital receivers to programmable processors.
Now what exactly is an FPGA Bridge and why is it an important design aid? To put this case in point, let me elaborate a design challenge I recently encountered while trying to interface an ADS5474EVM ADC Board and a TMS320C6455 DSK DSP Kit. The DSP required data from an analog sensor for processing. It activated the sensor by providing a capture pulse to it. The sensed analog data was digitized by ADS5474EVM ADC Board at 400 MSPS rate. TMS320C6455 DSK DSP Kit which required this digitized data from ADC for further processing was not able to sample the incoming data at such a high rate. So a need arose to implement a bridge circuit, that could sample data at 400 MSPS and store data equivalent to 20 ms (approx. 8 million samples) from the captured signal. The FPGA Bridge was designed to provide seamless interface between ADS5474EVM ADC Board and TMS320C6455 DSK DSP Kit. The FPGA bridge was a proof of concept that data at 400MSPS from ADC can be sampled at 200 MHz DDR rate by a Spartan 3a DSP (maximum operating frequency is 250 MHz), suitably stored and provided to DSP processor for further processing.
The above block diagram shows the top level interface diagram from ADS-5474 kit to FPGA Kit to TI-DSP 6455.
|Module Name||Clock Domain||Input Data Width||Output Data Width|
|ADC CAPTURE Module||In: adc_cap_clkOut: adc_cap_clk||14Bits data + OVR from ADC IC||32 Bits (2 Samples of ADC Inputs)|
|ADC_CAP_FIFO||In: adc_cap_clkOut: core_clk||32 Bits (2 Samples of ADC Input)||64 Bits to Memory Controller|
|Memory Controller||In: core_clkOut: core_clk||64 Bits Data from ADC_CAP FIFO||MIG controller (64Bits)|
|Memory Controller||In: core_clkOut: core_clk||64 Bits Data from MIG controller||64 Bits data to EMIF FIFO|
|MIG controller (DDR2 Controller Core)||In: core_clkOut: core_clk||64 Bits data to/from Memory Controller||32 bits DDR data to DDR2 Memory|
|EMIF FIFO||In: core_clkOut: core_clk||64 bits data from Memory Controller||32 bits data to EMIF Controller|
|EMIF Interface||In: core_clkOut: core_clk||32 Bit Data from EMIF FIFO||32 Bit Data to TI-DSP using EMIF Protocol.|
Main controlling FSM
Whenever FPGA is reset or powered up just completes a data transfer, FSM is in this state. FSM remains in this state until
When all the above three conditions are satisfied, FSM moves to Capture state and generates capture enable signal for ADC Capture module to start capturing the samples. In this state status register is updated on every clock.
FSM remains in the capture state until it receives capture done signal indicating that the required number of samples have been captured. If capture done was due to forced stop then an interrupt is generated to DSP. Capture enable is made zero and FSM jumps to ADC_transfer state. In this state status register is updated on every clock.
FSM remains in the ADC Transfer state until it receives transfer done signal indicating that the required number of samples have been transferred to DDR2 memory. An interrupt is generated to DSP if a bit corresponding to transfer done is set in Interrupt mask register. FSM jumps to Read Request state. In this state status register is updated on every clock.
FSM waits for DSP to write Read Request bit in the control register indicating that DSP is now ready to fetch data. When the Read Request bit is set to 1, FSM jumps to FIFO Ready state and generates the DDR Emif Transfer Enable signal to Memory module to start dumping data from DDR2 memory to EMIF FIFO. In this state, actual samples count register is written.
FSM waits until EMIF FIFO has 64 samples of data. FSM updates the status register indicating to DSP that data is in the FIFO to be fetched and also generates an interrupt if a bit corresponding to it is 1 in Interrupt mask register. In this state status register is updated on every clock.
FSM waits for DSP to write Read Sample Data bit in the control register indicating that the DSP has acknowledged FIFO Ready and FSM should continue to dump data from DDR2 memory to EMIF FIFO. FSM remains in this state until it receives DDR EMIF Transfer Done signal indicating that all the samples stored in the DDR2 memory has been transferred to EMIF FIFO. In this state status register is updated on every clock.
FSM waits until all the samples entered in samples count register has been fetched by ADC and then jumps to Idle state. FSM generates an interrupt indicating process complete if a bit corresponding to it is 1 in Interrupt mask register. In this state status register is updated on every clock.
FPGA acting as a bridge was not only able to sample data from ADC at 400 MSPS but was also simultaneously able to transfer and store that data, of maximum 16 million samples to DDR2 memory. Thus in this way DSP was able to process that large chunk of data without loss of any information by fetching it from DDR2 memory through FPGA EMIF interface.